Nonlinear conversion between analog and digital signals by a piecewiselinear process



Jan. 9, 1962 c. P. VILLARS 3,016,528

NoNLINEAR CONVERSION BETWEEN ANALOG AND DIGITAL SIGNALs EY APIEcEwIsE-LINEAR PRocEss Filed May 18, 1959 5 Sheets-,Sheet 1 FIG' lour/ur caos /74 Y our 3' 54 A D, i 24 D o2or/.v//vc 9 /02 *DP oso- WAVEj 22 i, [04, 03 -D40- soz/RCE /N C67: F04 D50- D] v 30 .97 /26 D5 73 l IX X $5 $012) wffaxf's s y s R Wm (Frs) (Fe) sw. m -l- 0 Beggi/gl Ffa '30munir/Y 'L /:5 807:5) 0 re;

l o X 'Y' 'Y X @(Ffg) 0 +En;

TABLE FOI? F F5 TABLE FOR FFg APPROX. ONE r/ME 5:9 SL07' l f ,j x x' xx' X X' X X' DELAY FF, FF2 FF5 FFl s n R S R R u D? 60 f1 el v 64 as 686/\ 52 /05 I /NVEA/ro/P C. l? VILLARS ATTORNEY Jan. 9, 1962 Filed May18, 1959 ONE FRAME TWO FOUR 5 Sheets-Sheet 2 FIG. 2

0 ref A 77' ORNE V REEBUS Jan. 9, 1962 c. P. VILLARS NoNLINEARCONVERSION 3,016,528 BETWEEN ANALOG AND DIGITAL SIGNALS BY APIECEWISE-LINEAR PROCESS 5 Sheets-Sheet 3 Filed May 18, 1959 VVTOR BcNv/LLARS Z g @L ATTORNEY Jan. 9, 1962 Filed May 18, 1959 OUTPUT CODEOUTPUT CODE may `SCALE Mcm/a: 5i /lao FACTOR -74 2 McmR- -l- /ooa ,ANALOG sla/VAL MA civ/rum:

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ANALOG S/GNAL MAGNITUDE C. P. VILLARS NONLINEAR CONVERSION BETWEENANALOG AND DIGITAL SIGNALS BY A PIECEWISE-LINEAR PROCESS 5 Sheets-Sheet4 X /5 CHOSEN FOP DES/RED APPROX/MAT/ON; THE/V:

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/NVENTOR C'. R V/LLARS wfg@ ATTORNEY Jan. 9, 1962 c. P. vlLLARs vNONLINEAR CONVERSIO 3,016,528 N BETWEEN ANALOG AND DIGITAL SIGNALS BY APIECEwIsE-LINEAR PROCESS 5 Sheets-Sheet 5 Filed May 18, 1959 n w L E ELE QQ lim 5.2m Mv .uw Il' L w .ut A i ATTORNEY United States Patent O N'NONLINEAR CONVERSION BETWEEN ANALOG AND LINEAR PROCESS Claude P.Villars, Gillette, NJ., assigner to Bell Telephone Laboratories,Incorporated, New York, N. Y., a corporation of New York Filed May 18,1959, Sen-No. 813,776 e 16 Claims. (Cl. 340-647) This invention relatesto digital transmission and, more specifically, to the nonlinearconversion of analog signals and digital signals, one to the other, by apiecewiselinear process.

The advantages of transmission by PCM (pulse code modulation), oneincreasingly important form of digital communication, over transmissionby PAM (pulse amplitude modulation), a. form of analog transmission, arewell known in the art and will not be examined at length here. For athorough exposition see, for example, the article The Philosophy of PCM,by Oliver, Pierce, and Shannon, in volume 36, Proceedings of the LRE.,pages 1324 to 1331 l(1948); H. S. Black, Modulation Theory, Van Nostrand(1933); and Etude sur la Modulation par Impulsions Codes, by applicant,appearing in Bulletinl Technique PTT (Post Telegraph and Telephone, aSwiss publication), pages 449 to 472 (1954). Sullice it to say that.transmission of information by PCM offers many distinct advantages overother methods in that the information is digital in nature and maytherefore be regenerated by repeaters judiciously deployed a'ong thetransmission path. The regeneration process substantially eliminates theaccumulation, in the course of transmission, of noise, crosstalk andother forms of signal degradation.

l Prior totransmission, encoding (i.e., conversion of the originalanalog information to a pulse code) is necessary in a PCM system; and ifthe digital information thus transmitted is to b e used in its originalform, upon its reception decoding is necessary.

Before encoding the original information, it is necessary that it bequantized. In the quantizing process the exact value of the informationat any instant is approximated by one of a number of discrete valuescommonly called quantum levels. The difference between the instantaneousvalue of the original information and the quantum level actuallytransmitted is called quantizing error and gives rise to what is knownvariously as quantizing noise or quantizing distortion. Quantizingdistortion is especially objectionabe and very often intolerable, whenthe instantaneous value of the original information is small, but isusually of no significance when the instantaneous value is large. Formore elfective transmission, it is therefore desirable to have morequantum levels available at low amplitudes of the signals in order tobetter dene these amplitudes, thus reducing the relative quantizingerror. Something is taken from the highervalued amplitude signals andgiven to the lower-valued amplitude signals. Consequently, Companding (averbal contraction of the terms compressing and expanding) may beadvantageously used in a quantizedsignal transmission system to balancethe undesirable effects of quantizing error.

DIGITAL SIGNALS BY A PIECEWISE- tion is the base two).

3,015,523 Patented dan. 9, 1962 It is the dynamic range of the originalinformation that is compressed in such a system. The dynamic range isreduced so that low amplitude samples of the original information areemphasized, i.e., effectively increased in amplitude, while thehigher-valued amplitude samples are de-emphasized.

Companding therefore serves a special purpose in quantized transmissionsystems in that it reduces the magnitude of the quantizing error for lowamplitude signals, where quantizing distortion wou'd be a seriousmatter, at the price of increased quantizing error for higher amplitudesignals, where increased distortion can be tolerated. Restated broadly,the purpose ,of the PCM compander is to reduce the quantizing impairmentof the original signal by, in effect, quantizing not on a uniform but ona nonuniform basis.

The `usual companding system incorporates as its main components acompressor at the transmitter and an expander at the receiver. Thesecomponents are normally separate units, the compressor being connectedexternally in tandem with the coder and the expander being connectedexternally in tandem with the decoder. See, for example,.The, Bell,Sysem Technicalv Journal, January 1948, volume 27, page 1, in which L.A. Meacham and E. Peterson describe such a system.

`PCM systemshave been devised, however, that combine the processes ofcoding and compression at the transmitting end and the processes ofdecodingand expansion at the receiving end. Such a system is disclosedby R. L. Carbrey in a copending application, Serial No. 631,806, tiledDecember 3l, 1956, which has since issued as Patent No. 2,889,409.Exemplary of the Carbrey invention is thetransmitting end of the systemin which a nonlinear encoder automatically compresses its input signalas it carries out its coding operation. B. D. Smith discloses a methodof nonlinear encoding by feedback methods in an article entit'ed CodingBy Feedback Methods which appearsrin volume 4l of the Prceedings of theI.R.E., at page 1053.

While the methods of conversion between analog and digital informationwhich have been disclosed by Carbrey and Smith have many advantages, theobjects attained by the presently disclosed method, and the featuresandadvantages thereof, constitute an important contribution to the eld ofPCM transmission.

It is for example, a principal object of the inventionv ln accordancewith the invention, nonlinear conver-A sion between analog and digitalsignals isv accomplished by a piecewise-linear process. Consider, forexample, the invention as embodied in the encoder. The input samples andoutput code of the encoder, though not linearly re'ated over the entirecoding range, are lconstrained to be so related over subrangesdetermined by the transition of predetermined digits in a permutationcode of base b (the base used to illustrate the inven- The digittransitions define breakpoints in a piecewiselinear compressioncharacteristic. Each segment of the characteristic defines a linearrelation between a specified range of analog signal magnitude and acorresponding range of digital code. The linear relation or scale factordefined by each segment in a particular quadrant is peculiar to thatsegment. The scale factor of a segment is here defined as the slope ofthe segment and is to be distinguished from the compression ratio of acontinuously nonlinear characteristic. The compression ratio may bedeiined as the ratio of the slope of the continuously nonlinearcharacteristic at the origin of the plot to the slope of thecorresponding linear characteristic passing through the origin.

It is a feature of the piecewise-linear system disclosed here that itcan be used to approximate almost any type of nonlinearity and yetretain some of the simplicity of linear systems.

The invention will be better understood from the following detaileddescription given in connection with the appended drawings in which;

FIG. 1 is a block schematic diagram depicting a piecewise-linear encoderwhich embodies the invention;

FIG. 2 is a plot of waveforms illustrating the operation of theembodiment of FIG. 1;

FIG. 3 is a so-called encoding ow diagram, also illustrating theoperation of the embodimentfof FIG. 1;

FIG. 4 shows the piecewise-linear encoding characteristic of theembodiment of FIG. l;

FIG. 5 illustrates a representative piecewiseelinear encodingcharacteristic having Vmore than one breakpoint in order to more closelyapproximate a given nonlinear function;

FIG. 6 is a partial schematic circuit which shows the manner in whichthe piecewise linearity of the characteristic of FIG. 5 may be achieved;and

PIG. 6A is a partial schematic circuit showing the various possiblecombinations and associated currents of the shunting resistors R27 andR2 of FIG. 6.

For the sake of brevity and simplicity the present disclosure willconcern the application ofthe principles of the invention to theencoding process only. This eX- pedient is believed justified, since itis well known that principles applicable to encoding are equallyapplicable in a straight-forward manner to the reverse process ofdecoding. Also, for ease of narration and understanding, theembodimentyillustrated in FIG; 1 has been considerably simplified inthat it converts analog information on a piecewise-linear basis to onlya four-digit code, and has an encoding characteristic (see FIG. 4)having simply one breakpoint or two linear segments per quadrant. Itshould be understood, however, that in the p-actice of the invention thecode may consist of any number of desired digits, the number beinglimited only by other considerations. The number of breakpoints which isused is determined not by any limitations of the invention, but ratherby the degree with which a specified nonlinear characteristic is desiredto be approximated.

In the description of the illustrative embodiment of FIG. l, referencewill be made at appropriate times to FIGS. 2, 3 and 4 as aids inunderstanding the process occurring in the circuit of FIG. l.

In FIG. 1 a message current is, plotted in FIG. 2(1),

is supplied to the input terminal 22 and thence to the summing circuit24. The summing circuit 24 combines the message current is with areference current i666, supplied by way of inp'ut lead 26. The manner inwhich the reference current-im is generated will be thoroughlyexplor'ed. Itlshould be noted now, however, that im is desired to be ofopposite signin respect to the polarity 6 of the message current iswithwhich it is to be combined.

Function of elements now4 be explained. The summing circuit'24 takes'the 4 sum of the input message current is, supplied by way of the inputterminal 22, and the reference current im,

supplied by way of the input lead 26, and conveys thisl sum to theamplifier 28. The resultant sum, the current im, is shown as waveform(2) in FIG. 2. The functions of the summing circuit 24 and the ampliiier2S may be combined in a Summing amplifier. In its amplified form, im isthen supplied to the input terminal s of decision circuit 30.

Decision circuit 30 is a Schmitt bistable or ipaflop circuit havingunity loop gain, and is here denoted as FP6. The stimuli which affectthe state of FP6 are tabulated in table 72 of FIG. l.V The state of FP6,it will be noted, is determined by the polarity of its input terminal s.This will be discussed at length in the description which follows. Foran unusually thoroughgoing article on the Schmitt circuit, see G. L.Swaflields article, The Schmitt Multivibrator, which appears at page 344of the July 1958 issue of WirelessY World.

Though Hip-flops PF1 to FP6 are shown in identical iiip-op convention,it should be understood thatPF6 is different in its purpose andfunction, and consequently in structure, from all the other Hip-flopcircuits of FIG. l, namely, iiip-ops PF1 to FP5. Each of the latterflipflops is of the conventional Eccles-Jordan type. As to each ofthelatter, when either of ,its input terminals s and r is impulsed, itwill remain in the state determined by the impulse until such time asthe other terminal is impulsed. In other words, as to llip-ops PF1 toFF6, a constantly present stimulus is not required to maintain either ofthe two possible states of equilibrium. Each of the output terminals -xand x' may be in either of two states, a 0 or 1, depending on the stateof the other output terminal. The binary terms l and 0 are usedrespectively to indicate the presence or absence of a stimulus orimpulse. Thus, when any of the x output terminals is in `the O state,its associated x' output terminal is in the 1 state.

It will be assumed that thek terminals x and x of the various ip-flopcircuits of FIG. 1 are in a certain state at the beginning of each codegroup and, hence, of the processnow to be discussed. Thus we will assumethat while the embodiment of FIG. l is at rest, all the x terminals ofthe Hip-flop circuits, with the exception Vof FP2, are in the 0 stateand, consequently, the terminals x are in the l state.

In each of the Hip-flop circuits the terminals s and r represent inputterminals to whichv stimuli are supplied and the terminals x and xrepresent the output terminals from which stimuli are derived. The inputterminal s may be thought of as the set terminal; and the terminal r maybe though of as the reset terminal, in Vthat the latter terminal returnsthe iiip-op circuit to its rest state.

It can be seen from a consideration of table '72 that when the inputterminal s of FP6 is at a positive potential, i.e., when the current imis positive, the states of the output terminals x and x willberespectively l and 0. When', on the other hand, the terminal s of FP6 isat a negative potential, the states of the output terminals x and x' arerespectively O and 1.

It should be noted that when any AND or ORY gate terminal or any switchenabling lead is connected to a circuit point ir1,the1 state, theterminal or lead will beenabled. v

The subsequent discussion will be facilitated, if, instead of referringto the output terminal x of a particular flip-dop, say FP6, as theoutput terminal x Vof liipflop circuit FP6, this terminal is `referredto simplyas terminal x(FF6) As was already mentioned above, the polarityflip-flop FF5 and the switch-enabling ipflops FP1 to PF4', unlike f thedecision Vflip-flop FP6, are of-,the conventional Eccles- It can beseenV -Ifrom Ya :consideration of Jordan type. y table 73 in FIG. 1 thatwhen the input terminalfsr(FP5) is impulsed, i.e., when the AND gate 32is enabled, the output terminals x(PF5) and x(FF5) are respectively inthe 1 and 0 states. When 4terminal x(FF5) is in the state, it can alsobe seen that the switch S5 is switcihed to the negative referencepotential source 49. It is not necessary that the stimulus supplied tothe input terminal s(FF) by the output lead of AND gate 32 be maintainedin order that the above-mentioned state of polarity flipflop FF5 remainunchanged. When the input terminal r(PF5) is impulsed, the states ofterminals x(FF5) and x(FF5) will be respectively 0" and "l" and theswitch S5 will be switched to the positive source of reference potential4S.

Each of the flip-op circuits PF1 to PF4z is a switchenabling element, asis FF5. Plip-flops FP1 to PF4 are used to control switches S1 to S4,respectively. The output terminals x and x of each of these flip-flops,excepting FP2, are respectively in the 0 and 1 states when the ip-fiopsare at rest, i.e., at the commencement of any frame or code group (seeFIG. 2). When the state of any of the flip-flops PF1 to PF4 is changedfrom its rest condition by an impulse supplied to its input terminal s,the state of its output terminal x will be a l and its associated switchwill be switched from ground to the reference current bus 56 in the caseof switches S1, S3 and S4, andfrom open circuit to ground in the case ofswitch S2. When the state of each of the x terminals of tlip-liops FP1,PF3 and PF4 is a 0, the switches S1-S4 will be positioned as shown inPIG. 1. It will be notedthat when this condition obtains, the outputterminal x(FP2) is in the 1 state. Conversely, when the state of each ofthe x terminals of flip-flops PF1, F133, and PF4 is a 1, the switchesS1-S4 will be positioned oppositely to the manner shown in FIG. 1. Notethat the output terminal r(FF2) will then be in the 0 state.

FIG. l depicts the AND and OR gates in conventional fashion. The ANDgates are each represented by a closed arc, the ofutput lead of the gateextending from the midpoint of the arc and the input leads beingconnected to the chord of the arc. See, for example, AND gate 50. The ORgates are also represented by a closed arc but are distinguishable fromlthe AND gates in that the input leads extend through the ch-ord of thearc to the are. See, for example, OR gate 52. Thus in the conventionused here, a gate is an OR `gate when its input leads are shown toextend through the chord of the are to the arc and is an AND gate whenits input leads extend only to the chord of the arc. As is well known,enablement of an AND gate requires universal concurrence of stimuli atits input leads. Thus, for example, enablement of AND gate S0 requiresthe concurrence of stimuli or ls, from x(FP6) and x(FP5). Enablement ofan OR gate, on the other hand, may be accomplished by supplying astimulus to any of its input leads. Thus, for example, OR gate 52 willbe enabled when either of AND gates 50 and 70 is enabled.

The timing wave source 40 supplies impulses to various points in thecircuit of FIG. l. The impulses are supplied periodically. ln FIG. 2(6),for example, it can be seen that the output terminal D2 of timing wavesource i0 supplies an impulse in the second time slot of each frame.Timing circuit 40 may be any of the many suitable timing signalgenerators so well known in the art. It may, for example, be of the typedisclosed at page 52 in volume 32 of Electronics (March 6, 1959), aMcGraw-Hill publication.

The functions and relationships between the resistors switched into andout of connection with the summing circuit input lead 26 by switches S1to S4 are more easily understood after a consideration of FIG. 4. FIG. 4fully shows that portion of the encoding characteristic of theembodiment of FIG. 1 that lies in the first quadrant. The

partially. Thecharacteristic, in accordance with the invention, ispiecewise-linear and is shown in its simplest form, in that it has butone breakpoint 86. Note that the characteristic approximates thecontinuously nonlinear characteristic 88.

Each linear segment of the piecewise-linear characteristic has its ownpeculiar scale factor. As was mentioned previously, the scale factor ofa segment is the slope of the segment. The scale factor of segment 90,for example, may be determined as follows. At the breakpoint 86 thequantum level represented by the code 1100 is +4 and the coordinateanalog signal magnitude is +2. Thus, the scale factor of segment 90 is2.0. By the same reasoning, the scale factor of segment 92 is equal to4/s.

Each linear segment of the characteristic defines a subrange of thepeak-to-peak encodable analog signal excursion. Thus, segment 90encompasses analog signal magnitudes lying between 0 and -l-2.` Itshould be understood that the breakpoint 86 need not occur where shown.The locus of the point is determined by the value of the current X,which is arbitrarily chosen for any desired approximation. Moreover, thebreakpoint 86 need not occur at the transition from 0 to l of the secondmost significant digit-the order of significance being from left toright-but may be chosen to occur at the transition 0f the third or eventhe fourth most significant digit. Therefore, before passing on to afurther consideration of the invention, the reader should understandthat the illustrative embodiment of PIG. 1 and its encodingcharacteristic, as shown in FIG. 4, are intended as very simpleillustrations of the invention.

The arrangement of the resistors in PIG. 1 is applicable only to a4digit code in which the first digit determines the polarity of thesignal and the next most significant digitrdeterrnines the breakpoint ofthe coding characteristic in either the rst or third quadrant. The Valueof the resistor RX is arbitrarily chosen to determine the location ofthe breakpoint 86. The current flowing through RX has been denotedsimply as X, since it is an independent and arbitrarily chosen quantity.Note that if the piecewise-linear characteristic breaks at more than onepoint in each quadrant, there will be correspondingly more resistors ofthe ktype exemplified by RX and that these additional resistors willdefine the loci of the additional breakpoints. Thus, if more breakpointswere desired, We could have the independent and arbitrarily chosenquantities X1, X2, X3, and so forth (see FIG. 5).

The combination of resistors R1 and R2 will give the desired change ofscale factor when the breakpoint 86 is reached. It can be seen in PIG. 4that when the logic elements of FIG. l have determined that the messagecurrent is lies within one of the subranges encompassed by the linearsegments 90 and 92, that an appropriate scale factor must be used. Achange of scale factor in the simple illustrative embodiment of PIG. 1is ultimately accomplished by resistor R2. When switch S2 is switched toground and the reference current lead 26 is connected to either of thereference potential sources 48 and 49, the encoder has determined thatthe message current is lies within the subi-ange encompassed by segment90. lt can be seen in FiG. l that when the encoder is in its restposition, as shown, that the reference current lead 2o is connected toneither of the reference potential sources 43 and 49.

It is well to notice that reference currents fed through R3 and R4 areultimately fed into a low impedance summing point represented by summingcircuit 24. This summing point may be considered as essentially atground.

lf, therefore, resistor R1 were not positioned serially, as shown, thenthe effectiveness of`R2 as a shunt path to reduce the amount ofreference current fed to summing circuit 24 would be greatly reduced,since the currents i3, 1'35, i4 and i4* would then prefer theabove-mentioned summing point, virtually excluding the path presented byR2. -In otherwords without R1, reference currents fed from R3 and R4would avoid R2 in favor of the much lower impedance represented vbysumming circuit 24.

AS was already mentioned, resistor RX is chosen to approximate a desirednonlinear characteristic. The current X, flowing through resistor RX,establishes the breakpoint 86 of the piecewisedinear characteristic.Now, in order to render the relationship between currents within each ofthe linear segments 90 and 92 a binary relationship, it is necessarythat all resistors other than RX, R1 and R2 be related to each other inpowers of two and be chosen to conform to the established breakpoint 86.ln the simplified embodiment of FIG. l, the other.resistors are R3 andR2. Refer to FIG. l. The value of R3 is chosen so that the current i3,as it is fed into the surn ming circuit input lead 26, has the followingvalue:

where max is the maximum encodable positive excursion ofthe messagecurrent is. The value of resistor R4 is then chosen so that t4 equals 2In other words, the value of resistor R4 is twice that of resistor R3.

If the code used were to consist of more than four digits, additionalresistors of the type exemplified by R3, and R4 would be added andsimilarly incorporated in the circuit. The additional resistors, say RYand RZ, would be binarily related to resistors R3 and R4, Thus, thehypothetical resistors RY and RZ and the resistors R4 and R3 could bearthe relationship (RY:RZ:R. 3:R3) as (8:4:2:1). l v

The value of R2 is not arbitrarily chosen. The scaledv down counterpartsi3* and i4* of the .currents i3 and i2 are supplied to summing circuit24 only when the resistor` R2 is connected to ground. When R2 is soconnected, it shunts to ground a predetermined amount of any currentwhich is being supplied by way of R3 or R4. The shunting resistor R2 .istherefore chosen so that the scaled-down, star (ci) values i3?e and ifof the binary-related currents i3 and i4 divide the current axis of thefirst segment from the origin-the segment 9th-in binary fashion, just asi3 and i., binarily divide the current axis of segment 92.

R2 is thus chosen so that it vpreserves the binary ratio between i3 andi4 on a scaled-down basis to conform to the subrange defined by segment90. Stated mathematically, the value of R2 is chosen so'that:

i (tm-x) Notewell, however, that the above-stated general relationshipbetween the non-star and star currents is valid only for the verysimplified piecewise-linear characteristic illustrated in FG. 4, i.e.,it is valid only for piecewise-linear characteristics having onebreakpoint per quadrant. f

lt can be seen, then, that when the value otR2 is chosen as explainedabove, f

Thecu'rre'nt axis of segment90 is thus broken up in'binary fashion bythevarious possible combinations of thev star Yes (*) currents i3* andigt'. An example of the generation of one of these various possible`combinations will be given. If at a particular time the message currentis is` such that it is necessary to generate the star currents i3* and1'41, the switch S2 will connect the'shunting re sistor R2 to ground,and resistors R3 and R4 will be co n nected to the reference current bus56 by switches 83j and S4, respectively.

lt should now be apparent in the illustrative embodi` ment chosen todescribe the invention, that it is necessary;

for the generation of any star (it) current that the rie-v* both beconnected'` In the illustrative embodiment of FIG. 1,. the resistors RXand R2 are connected to ground during' the first and fifth time slots ofany code group (see FIG. 2) and are connected to ground at other timesonly when s the generation of star current is necessary. It should l benoted that when any-of the star currents, isneeded .i

sistor RX and the shunting resistor R2 to ground.

as a component of the reference current im, that theL current X, whichdefines the whole of the subrange off which the star ("i) currents arecomponents, will not be; generated. This explains the reason whyresistor RX. is, grounded, i.e., taken off bus 56, whenever thegeneration of star currents is required. The manner in which the variouscurrents are generated will be clear when the operation of theillustrative embodiment of FIG.. 1 hasl from juncture 100, for eachpossible combination of connections of R3 and R4.

The relationships between the currents max, X, i3, i4, 3*, and i4* willperhaps be more meaningful if these. currents are expressed numericallyin the units of analog signal amplitude used Vin FIG. 3. Assume, then,that imm-:7.0 units of current. Assume, further, that the breakpoint 86of the piecewise-linear vcharacteristic of FIG. 4 is chosen so that X=2.0 units. Then;

,:rtm- X) :n-2) :2.50 units ffl-2X1: 1.00 unit,

and

Notethe relationship between each code value used in FIG. 3 and thecorresponding analog current amplitude. Within each segment thisrelationship defines the scale factor of the segment. The compression ofthe dy-V namic range of the message currents is thus apparent. v Forexample, the code 1100 (having a code value 'of +4) As another example.,consider the code 1110 which khas, a code value. of +6 and is used torepresent a messagecurrent. amplitude of +4.50, This relationship isdefined by ablesen .9 the second segment, segment 92 of FIG. 4. Thescale factor of the segment is therefore four fifths As an example ofjust one variation from the very simple illustrative embodiment of FIG.1, supposewhile still retaining a single breakpoint per quadrantthat aS-digit code were used. Then another resistor, say R0, would be requiredafter R4. Since only one breakpoint has been assumed, only onearbitrarily chosen resistor is needed. Hence, RX may be retained. Inthis hypothetical example, the following relationships would hold true:

i being the current which would pass through the newly added resistorR0. Then the following relationships would also hold true:

X @er X a*=r X 10am... 8

From the above relationships it can be seen that the addition of furtherdigits to the code will result in a iiner binary breakdown of eachsubrange of the piecewiselinear characteristic.

The encoding process The operation of the simplified embodiment of FIG.1 will now be described. In the description which follows, referencewill frequently be made to the timing diagram of FIG. 2 and the encodingflow diagram of FIG. 3. As previously alluded to, the plot of waveformsin FIG. 2 is divided into periodically recurrent time frames, eachconsisting of five time slots which accommodate one code group. Eachtime slot is therefore also periodically recurrent. Though theillustrative encoder of FIG. 1 generates a 4-digit code, tive time slotsare provided. The tifth time slot is employed so that the outputterminal D5 of timing circuit 40 may reset the terminals x(FF1), x(FF3),and x(FF4) to "0 before each frame begins. Note that terminal x(FF1) inturn resets the terminal x(FF2). It is not necessary, however, that afifth time slot be used. For example, it is not uncommon to provide aso-called guard space between each time slot. When such a space isprovided, the interval between the last time slot of a time frame andthe tirst time slot of the immediately following frame may be used toserve the purpose of applicants iifth time slot.

It is appropriate to note that the switching impuses of FIG. 2 need notbe entirely positive. As a practical matter they are, in fact, usuallynegatively biased. This expedient will ordinarily result in betterswitching of elements such as diodes and transistors.

As was previously mentioned, the operation of the encoder of FIG. l isregulated with respect to time by the timing circuit 40. Each of theoutput terminals of timing circuit 40 is connected to various points inthe encoder to provide impulses in synchronism with the occurrence of aparticular time slot. Thus, for example, the output terminal D1 oftiming circuit 4t) will provide an impulse to AND gate 54 upon eachoccurrence of time slot l.

The other aid indescribing the operation of the encoder of FIG. 1,namely the encoding yflow diagram of FIG. 3, consists of two parts. Theleft-hand portion ofthe diagram is :a tabulation of a binary coderepresenting the units of amplitude of the message current is. Aspreviously mentioned, each element of the code may be either a l or 0.In each code group the elements are written from left to right indescending order of significance, i. e., the most significant digit isfurthermost to the left. It indicates the polarity of the messagecurrent is. When the message current is is positive, the polarity digitwill always be a 1 and when this current isnegative the polarity digitwill always be a 0.

For example, as can be seen in FIG. 3, if the amplitnde of the messagecurrent is equals +4.5 units, the code which will be used to representthis amplitude will be 1101. Since the code group 1101 has a code valueof 5, the compression of the dynamic range of the message current s isapparent. On the other hand, if the amplitude of the message current isis -4.5 units, the code group used to represent this amplitude is theprime of the code group used to represent +4.5 units. Thus, 4.5 units isrepresented by the code group 0010.

When a code group is primed each element of the group is changed to itsbinary opposite. This can be seen from a comparison of the code groupsrepresenting +45 units and -4.5 units. The functions of the l and the 0in a code are thus reversed in a corresponding prime code. In theillustrations chosen, for example, 1101 has a code value of +(22+0+20)or +5 code units, whereas the code group 00110, the prime of 1101, has acode value of -(22+0+2) or -5 code units. It should be understood,therefore, that a prime method of differentiating between positive andnegative code Values is used in FIG. 3. This method should bedistinguished from the often-used reflected method of differentiation inwhich the tabulation for negative values is, with the exception of theiirst digit, an image, as it were, of the tabulation for positivevalues.

The right-hand portion of the encoding ow diagram of FIG. 3 illustratesthe process by which the amplitude ofthe message current is at anyinstant of time is approximated by a summation of the components ofreference current im. That negative values of the reference current imand negative values of the code lie across from each other, as do therespective positive values, should not be construed to mean that if themessage current s is negative that negative values of the referencecurrent tref shall be employed. On the contrary, when the rnessagecurrent is is positive, it is desired that the reference current im benegative in the trial and error process by which the amplitude of themessage current is is approximated by the digital code. Now that FIGS. 2and 3 have been explained, the operation of the illustrative embodimentof FIG. 1 may be approached with greater understanding.

It will be much more meaningful if representative numerical amplitudesof the message current is are used in the discussion which follows thanif the operation of the circuit is approached in the abstract.

Hypothetical case I As a irst example, it will be assumed that themessage current is is equal to +7.0 units of analog current amplitude.The operation of the encoder for such a value of message current isillustrated by those portions of the 20 waveforms of FIG. 2 lying withinframe two. Thus, portion 81 of the message current is in FIG. 2(1) isequal to +7.() units.

At the commencement of time slot 1, no reference current im is fed intothe summing circuit 24. This is because the reference current lead 26 isnot connected to the reference current bus 56 by any of the switches S1,S3, and S4. The input current im of amplitier 28 therefore representsthe message current is only. Since is is positive, the potential of theinput terminal s(FF6) will be positive. Consulting Table 72, the readerwill note :tively and f1. tllluctrates the operation of the polarityiiip-ilop FFS, the

'1".1 that when MFFS) is positive, the'outputterminalsxtFF) and x'(FF6)are respectively in the 1 and G states. Also at'the commencement of timeslot l, the states fof the output terminals x(FF5) and x(FF5) arerespec- Consulating the Table 73, which @feeder will note that Vwhenx(FF) is, in the 1 state YKthat the polarity switch S5 connectsthereference current bus 56 to the positive source ,et referencepotential 48. The inputs of AND gates ,50 are connected to the terminalsMld-F6) and x'tFFg). Since these terminals are both in the l state atthe commencement of time slot i, .AND gate 50 will be enabled. The ORgate 52 will Aturn beenabled, thus enabling the inhibit bus 5S.

'There is a concurrence of impulses at the inputs 'of AND gate 54 fromthe terminal lx(FF6) and the terminal D1 of timing Awave .source 40.Hence, AND gate V54 is enabled 4and the tirst digit 'of .the code groupwhich vwill v.represent the amplitude ofthe message from is is vproducedat'the output terminal `'74. Because AND gate 54 Was enabled, this digitis a 1. Being Vthe most sig- .nicant digit, it indicates thatthelmessage current is is positive (see FIG. 3). Oipthe live terminalsD1 to D5 of timing wave source 40, D1 is the only one which .supplies4an impulse during time slot l.

During time slot 1, the flip-flops PF1, .FF3, and FF., lare in theirrest states, as will beseen. The output terminals x and x of eachofthese ip-ops are respectively fin the 0 and 1 states. Switches S1, S3and S4 are thus all switched y.to ground,.since their associated x ter-'.tninals are `each in the l state. `The reference current flaus 56 istherefore disconnected from the summing cirfcuit input lead 26.

The rest condition of the reference current circuit 99 @during time slot1 will now be explained. As was men- 'tioned previously, the inhibit bus58 has been enabled by AND gate 50 and, consequently, by OR gate 52.During time slot l, however, enablement of the inhibit bus 58 is of noconsequence since the output terminals x(FF1) l `and x(FF1) are alreadyin their rest states 0 and 1,

respectively. Moreover delay circuit 59, which has a delay periodsubstantially equal to one time slot, depending upon the cumulativedelay experienced in other elements of the circuit, will postpone theinhibitive eifect of lbus .58 until time slot 2 of frame two. Sincex(FF1) is in the 0 state, the switch S1 is connected to its groundterminal as shown. No current tiows from the reference current bus S6through RX and thence into the summing circuit 24. The current X istherefore zero.

Since the terminal s(FF2) is connected to the terminal x(FF1), whichterminal is at present in the l state, the output terminal x(FF2) is inthe l state and the switch S2 is enabled, connecting shunting resistorR2 to ground.

Though shunting resistor R2 is now connected to ground, it isnevertheless of no elect in producing the star currents previouslymentioned, since no current lows into junction 100 during the time slot1.

Again, the fact that the inhibit bus 58 is enabled has no effect on thestate of flip-flop FF3, sincerAND gate 84 is not enabled unless impulsesare concurrently supplied from the output terminal D4 of timing wavesource 4t) and from inhibit bus 61. Nor is OR gate 68 enabled unless animpulse is supplied from either AND gate 34 or the output terminal D5 oftiming wave Vsource 4d. Furthermore, the input terminal s(FF3) will notbe enabled until an impulse is supplied from the'output terminal D3 oftiming wave source 40. The state of output terminal x(FF3) is therefore0, switch S3 Vis at `rest in its ground position, and the resistor R3 isnot connected to rthe reference current bus S6. Thus, neither of` thecurrents i3 and i3* is supplied during time slot 1.

As in the Vcase of Hip-flop FF3, the input terminals s and r of FF.;lare presently both in the "0 state and, con- Y sequently, theterrninalsx(FF4) and x(FF4) are respectively in the "0 `and 1states.V Switch S4 istherefore `ming circuit 24. The current X, as can be seen in FlG. 3,

has an amplitude of negative 2.0 units, and when it is added to the 7.O` units of amplitude of the message current is, the resultant currentim is equal to +5.() units. Acj cordingly, the potential at StFFG)remains positive vand the states of the Output terminals MFE-6) andx"(FF6) `remain respectively l 'and 0;

A very short period of time before the commencement of time slot 2, theinput lead 97 of AND gate 32 is impulsed by an impulse which wassupplied to delay circuit 82 by the terminal D1 of timing circuit 4dduring the first timeslot.

The vdelay'provide'dby delay circuit 32 in eilect'presets Vpolarityflip-ilop FF5 which, in'turn, insures that im will be of proper polarityat the commencement of `time slot 2. Since the output terminal x(FF6)was also in the l state at the time input lead 9'7 of AND gate 32 wasimpulsed, the input terminal .(FF5) was impulsed 'at that time. tlopFF5. When s(FF5) is impulsed, the output terminals x(FF5) and x'(FF5)are respectively in the 1 and 0 states and the switch S5 is switched tothe negative source of reference potential 49.

Since the terminals x(FF6) and x(FF5) are not concurrently inthe l stateduring 'time slot 2, AND gate 50 is disabled during this interval. ANDgate is also disabled since the terminals `x(FF6) and x(FF5) also arenot concurrently in the l state during 'time slot 2. VInhibit bus 58 istherefore disabled. The switch S1, which was previously mentioned tohave switched the resistor RX to the yreference current bus 56 inordertosupply the current X to summing circuit24, .is enabledY at thecommencement of time slot 2 by an impulse supplied to s(FF1) from theterminal D2 of timing circuit 4i). The reset terminal r(FF1) is notimpulsed during time slot 2, since AND gate input lead 60 is disabled.Now that the output terminals x(FF1) and x(FF1) are respectively in the1 and 0 states, the input terminals s(FF2) and r(FF2) will berespectively in the 0 and 1 states. Thus the state of output terminalx(FF2) is 0, switch S2 is disabled, and resistor R2 is connected to theopen circuit terminal 44.

As in the case of the input terminal r(FF1), terminal 1(FF3) is in the"0 state since the juncture 105 is disabled. The output terminal x(FF3)therefore remains in its rest state, i.e., the 0 state, switch S3remains disabled, and resistor R3 remains connected to ground. Neitherof the currents i3 and i3* is therefore supplied by way of R3. Sincejuncture is presently disabled, the state of flip-flop FF., remainsunchanged and the output terminal x(FF4) is still in the 0 State. SwitchS4 remains connected to its ground terminal and neither of the currentsi4 and i4* is supplied by way of resistor R4.

Accordingly, the only current supplied to the summing circuit 24 by wayof the reference current lead 26 during time slot 2 of this hypotheticalexample, is the current X which is equal to negative 2.0` units. Thecurrent im, as previously mentioned, is therefore equal to -|-,5.0units, the output terminal x(FF6) is in the l state, the AND gate 54 isenabled by a concurrence of impulses from terminal x(FF6) and terminalD2 of timing wave source 40, and the binary digit "1 is supplied to theout-- put terminal 74. The accumulated code at the end of Vtime slot 2is therefore 1l.

YDuring time slot 3, it will be seen that the current i3 equal tonegative 2.5 units (see FIG. 3), is added to the current X to increasethe reference current im to negative The combmation of the messagecurrent i,1

4.5 units. (7.() units) and the reference current im (negative V4.5

Consult table 73 which relates to the polarity flip-r units) in summingcircuit 24 yields an amplitude of im equal to +25 units. Input terminals(FP6) is therefore still at a positive potential and the states of theoutput terminals x(PP6) and x(PP.-,) remain unchanged, i.e. remainrespectively l and 0. The states of the output terminals x(PP) andx(PF5) also remain unchanged, since the state of polarity flip-lop PP5will not be changed until the commencement of the fifth time slot.Therefore, there is not a concurrence of impulses at the respectiveinputs of either AND gate 50 or AND gate 70. Accordingly, inhibit bus 58remains disabled.

The state of flip-flop PF1, and therefore the position of switch S1,remain unchanged. The resistor RX is still connected to the referencecurrent bus 56 and the current X is supplied to the summing circuitinput lead 26. So, too, the state of nip-flop FP2 and the position ofits associated switch FP2 remain unchanged and, consequently, theshunting resistor R2 is still connected to th open circuit terminal 44.y

The input terminal s(PP3), however, is impulsed at the beginning of timeslot 3 by the output termnal D3 of timing wave source 40, so that theoutput terminal x(PF3) now assumes the 1 state and enables the switchS3. Enablement of switch S3 connects resistor R3 to the referencecurrent terminal 66 and thence, by way of reference current bus S6 andpolarity switch S5, to the negative potential source 49. Since resistorR2 is connected to the open circuit terminal 44 of switch S2, no currentsupplied by Way of resistor R3 is shunted through resistor R2 and,consequently, the current i3 (equal to negative 2.5 units) is added tothe current X (equal to negative 2.0 units). The summation of thesecurrents yields a value of ref equal to negative 4.5 units. The state offlip-flop PF4 is unaltered during time slot 3 and, hence, as was trueduring time slot 2, no current is supplied by way of resistor R4.

As was previously mentioned, the negative 4.5 units of currentrepresented by iref are added to the 7.0 units of current represented bythe message current is to yield a value of im equal to 2.5 units. Theconsequent concurrent of impulses from the output terminal x(PP6) andthe terminal D3 ot' timing wave source 40 enables AND gate 54 and abinary digit 1 is supplied to the output terminal 74. The accumulatedcode at the end of time slot 3 is therefore 111.

As will be seen from the following discussion of the processes occurringduring time slot 4, the value of im remains positive. The potential ofterminal s(PF6) is therefore positive and the states of output terminalsx(PP6) and x(PP6) remain respectively 1 and 0." Since the outputterminals 'x(PP5) and x(PP5) also remain unaltered, neither of the ANDgates 50 and 70 is enabled and, consequently, the inhibit bus 58 remainsdisabled.

Of the Hip-flops PF1 to PF4, the only one that will be atected duringtime slot 4 will. be nip-flop PF4. A change of state occurs in nip-flopPF4 by virtue of an impulse supplied to its input terminal s from theterminal D4 of timing wave source 40. The output terminal x(PP4) thenassumes the 1 state, switch S4 is switched to its reference currentterminal 95, and current ows through resistor R4 by Way of the referencecurrent bus 56 and the negative-potential source 49. The current i4,equal to negative 1.25 units (see PIG. 3), is consequently supplied tothe reference current lead 26 and added to the preexisting currents Xand i3 to yield a value of im equal to negative 5.75 units. The negative5.75 units of im are combined with the 7.0 units of is in summingcircuit 24 to yield a value of im equal to 1.25 units.

The AND gate 54 is thus enabled by a concurrence oi' impulses from theoutput terminal x(PP6) and the terminal D4 of timing wave source 40, anda binary digit l ld completes the coding process for the hypotheticaleX- ample of +7'.0 units of message current is.

During time slot 5 the encoder will be prepared for the next codingprocess. The input terminal s(PP6') is no longer positive since themessage current is goes to zero and the reference current im isdiscontinued. The reference current im ceases, since an impulse issupplied to each ofthe terminals r(PP1), 1*(PF3), and r(PP4) from theterminal D5 of timing wave source 40. Accordingly, each of the namedlip-ilops changes state so that its x output terminal is the 0 state andits associated switch returns to its ground position. At the same timean impulse is supplied to terminal r(FP2) by way of terminal x'(FP1).The output terminal x(PP2) thereby assumes the l state, switch S2 isenabled and resistor Rz is connected to ground. Also, during time slot5, the polarity fiip-op PP5 undergoes a change of state by virtue of animpulse supplied to its r input terminal from the terminal D5 ofvtimingwave source 40. The states of the x and x' output terminals of each ofthe flip-flops PF1 and PP3 to FP6 are therefore respectively "0 and "1immediately preceding the commencement of the next following frame. Thestates of terminals x(PP2) and x(PP2), on the other hand, arerespectively "1 and "0 at this time.

Hypothetical case II As a concluding example of the operation of theillustrative piecewise-linear encoder of PIG. l, it will be assumed thatat the commencement of the rst time slot of frame three of FIG. 2 thevalue of the message current is is negative 1.5 units of analog currentamplitude. The behavior of waveforms (l) to (20) of PIG. 2 during framethree is pictorially representative of the operations now to bediscussed.

As in the previous example, during the first time slot no referencecurrent im is fed into the summing circuit 24. Consequently, the currentim is representative of the message current s only, and, for thishypothetical example, will be negative.

It has been assumed throughout the specification that no phase reversaloccurs in the amplifier 28, though, needless to say, this assumption isnot necessary. Refer to table 72: since the current im is negative, thepotential at s(PF6) is negative and the states of terminals x(PP6) andx(FP6) are respectively 0 and 1. Until the expiration of the delay incircuit 82, the polarity ipop PP5 will remain in the rest state itassumed during time slot 5 of the next previous frame. Thus therespective states of the output terminals x(PF5) and x'(PP5) are also "0and ul at this time. Neither of the AND gates 50 and 70 is thereforeenabled since there is not a concurrence of the necessary input pulsesat either of tlligese AND gates. inhibit bus 58 is consequently disa eSince the state of output terminal x(FF5) is at rest, i.e., is a 1, theswitch S5 is also at rest and, consequently, is switched to the positivereference potential source 48. That the positive source 48 is connectedto the reference current bus 56 at this time is of no consequencebecause all of the switches S1, S3 and S4 are disconnected from theirreference current terminals. So, too, it is of no consequence, as waspreviously mentioned, that at this time resistor R2 is shunted toground, since no reference current is thereby diverted.

AND gate 54 is disabled since terminal x(FF6) is in the 0" state and,consequently, there is not a concurrence of impulses from the terminalx(PF,-) and the terminal D1 of timing wave source 4i). The binary digit0 therefore appears at the output terminal 74 and constitutes lthe iirstelement of the code group to be generated. Since the digit "0 is themost signicant digit of this code group, it indicates that the messagecurrent is is negative in polarity.

It will be noted that the portion of the encoding characteristic, whichrelates to the process occurring in re- 15 sponse'to the hypotheticalmessage current of value nega# tive 1.5 units, is the segment 91 of FiG..4, which segment is only partially shown. t

Immediately preceding the commencement of time slot 2, the delay circuit82 supplies an impulse to AND gate 32; but this is of no avail since theoutput terminal x(FF6`) is in the "0 state at this time. Consequently,AND gate 32 is not enabled and the polarity' flip-flop Eidg remains inits rest state. This sequence of events determines tliatthe referencecurrent needed in the trial and error approximation of the messagecurrent is must be of positive polarity. In response to thisdetermination, the switch S remains in its rest state. The refer-V encecurrent bus 56 is, accordingly, appropriately connected to the positivereference potential source 48.

The input terminal s(FF1) is impulsed at this time by the terminal D2 oftiming wave source 40. The output terminals x(FF1) andvx'(FF1) arechangedfro'm their rest states 'and are now respectively in the "1 and0* states. The switch yS1 :is therefore enabled and is switched to its"reference current terminal 42. The current X (of value +2 units)then-flows through resistor RX, When x(FF1)vwas switched from the 0state to the l state, the input terminal r(IFF2) was impulsed. Theyoutput terminal x(FF2) was thereby changed from the l to the 0 stateand switch S2 was disabled, in turn causing shunting resistor R2 to beconnected to the open circuit terminal 44. Since the reference vcurrenttref, consisting solely now ofV the current X, has a value of +2 units,when it is combined with the message current is, the resultant currentim will have a value of +0.5 unit. The input terminal s(FF6) willtherefore be at a positvepotential so that the outputtermiuals x(FF6)and x(FF6) will change state, assuming the "1 and O states re-Aspectively. At this point in time it is too late, as has already beenseen, to enable AND gate32, since the impulse now available at terminalx(FF6) does not 'concur with the impulse previously supplied by delaycircuit 82. The state of polarity il'ip-tlop FFB therefore remainsunaltered.

Since there is a concurrence of impulses from the output terminal x(FF6)and the terminal D2 of timing wave source 40,'AND gate 54 is now enabledand it accordingly supplies an impulse, i.e., binary digit 1, to theoutput terminal '74. The accumulated code at this time is therefore .01.

It will be recalled that codes representing negative values of themessage current s are here primes of codes representing correspondingpositive values of the current is. Thus, the present accumulated code0l. means that the encoder has up to now determined that the messagecurrent is is (l) negative, and (2) is less in absolute magnitude than4.0 code units, or, considering the scale factor of two and expressingthe code units in analog units, is less in absolute magnitude than 2.0analog units.

During time slot 3, the following operations take place:

The switch S1 is immediately disabled so that the flow of Y current Xmay be discontinued. This is necessary because, as has been seen, it wasdetermined that the absolute magnitude of the current X (2.0 units) wasgreat- Yer than the absolute magnitude of the message current S (1.5units), which discrepancy causes the current im to become positive by0.5 unit. Y

The switch S1 is disabled as follows: At the commencement of time slot 3there is a concurrence of impulses at the inputs of AND gate 62 from theterminal 'D3 of timing wave source 40 and from the inhibit bus l5.1.Notice that the present inhibitive state of bus 61 is due to thepostponement of the inhibitive'state-of bus .58 byY delay circuit 59.rIt will be recalled that the output terminal VMFH) was changed to the "1state when the current im became positive during time slot 2. Theimpulse thus supplied by the terminal XCFFG) in concert d with theimpulse supplied by the output terminal #(75125) v.enz'tbled the ANDgate 5.0, 4the 4OR gate 52, andiinally 16 the inhibit bus 5S. Delaycircuit 59 thereupon proceeded to delay the inhibitive eiect of bus 5S.Thus there is a concurrence of impulses at the AND Vgate 62 at thecommencement of time sldt 3, AND gate 62 is enabled as is OR gate 64and, iinally, the input terminal r(FF1) is impulsed causing flip-ildpPF1 to change state. This change of state causes the output terminalx(FFl) to revert to its "0 state, thereby disabling the switch S1, Y Theimpulsing of the input terminal r(FF1) also causes the output terminalx(FF1) to assume the "l state, thereby changing the state of ip-op FF2by way of its input terminal s. The result is that the output terminalx(FF2) is now in the l state, the switch S2 is Yenabled and theshuritingresistor R2 is connected to ground. Ast

the switch S3 Ito be switched to its reference current terminal 66.Reference current from the source du new 'finds a pathhbywa'y ofreference current bus 56 through the resistor R3. l Some of thiscurrent, as'was previously mentioned, will be Ydiverted to ground by wayof shunting resistor R2. What remains of this current will be thecurrent i3* (having, here, a value of 1.0 unit) and this remainderfwillconstitute the reference current im.

Upon summing Ythe current i3* and the message lcurrent is insumming-circuit 24, 'the resultant current im isfound to have a value ofnegative 0.50 unit. The input terminal s(FF2) is, therefore, at anegative potential and the states of output terminals x(FF6) and x(FF6)are respectively 0 and 1. Although an impulse is supplied to the input102 of AND gate 54 by the terminal D3 of timing wave source 40, none issupplied to the in- ,put 104 bythe terminal x(FF6), since the latterterminal is now in the "0 state. Accordingly, AND gate 54 dicates thatthe absolute code value which will be used to y represent the messagecurrent iS is less than 4,0 but greater than or equal to 2.0 code units.This should not be confusing, as it will be recalled that thescalefactor of the segment 91 of the piecewise-linear character-l istic ofFIG. 4 yis 2 to l. Thus, when speaking in terms of code values, it issaid that the absolute code Value is less than 4.0 but greater than orequal to 2.0 code units, it should be understood that this is equivalentto saying that the absolute magnitude of the message current is is lessthan 2.0 but greater than or equal to 1.0 unit of analog currentamplitude. Y

Since the respective states of the terminals MFI-T6), x'(FF6)`, x(FF5),and x(FF5) were 0," 1, 0, and 1, at the termination of time slot 3,neither of the AND gates 50 and 7u was enabled. Thus, inhibit bus 58 wasdisabled. At the commencement of time slot 4, therefore, inhibit bus 61isv also disabled. Accordingly, when an impulse is supplied to junction104 by the terminal During this time the state of hip-flopV FP2 hasremained v unchanged so that the shunting .resistor R2 is stillconnected to ground. Accordingly, the current supplied by. way ofresistor R., to the junction 100, will be partly diverted to ground byway of shunting resistor R2 and partly supplied by way of the seriesresistor R1 to the sum- 17 f ming circuit reference current lead 26.That part of the current fiowing through R4 which is not diverted t0ground by way of shunting resistor R2 is here denoted as the current i4*and, for the sake of illustration, is given the value of 0.5 unit inFIG. 3. The reference current im therefore now consists of thecomponents i3* and if and has a value of +1.5 units of analog currentamplitude. When this value of reference current im is combined with thenegative 1.5 units of the message current is, the resultant current imis zero.

During time slot 4 the inputs I02 and 104 of AND gate 54 were notconcurrently impulsed since the state of output terminal x(FFG) was a 0.Therefore, AND gate 54 remains disabled and the binary digit 0 appearsat the output terminal 74. The accumulated code at this point in time isconsequently 0100 and stand for a code value of negative 3.0 code units,i.e., -(|21-}-20). As stated above, this code value corresponds to thenegative 1.5 analog current units of message current is. Thiscorrespondency is due to the scale factor two of the third quadrantsfirst segment, segment 91 (not fully shown). of the piecewise-linearcharacteristic of FIG. 4.

As in the previous illustrative example, where tht message current ishad a magnitude of +7.0 units of analog current amplitude, the fifthtime slot is used to clear out the encoder. The clearing out processinvolves the resetting of fiip-fiops FF1 to FF5 and ensures that at thecommencement of the first time slot of the next succeeding frame or codegroup, the output terminals x and x of these flip-fiopscircuits will berespectively in the 0 and 1 states. This resetting of the flip-flopcircuits in turn ensures that the switch S5 is connected to the positivesource of reference potential 48 (as shown) and that the switches S1 toS4 connect their associated resistors to ground (as shown).

FIGURES 5, 6, and 6A FiG. 5 has been included merely to show one of themany types of piecewise-linear encoding characteristics which may beobtained in accordance with the invention. The encoding -characteristicof FIG. 5 has three breakpoints determined by the arbitrarily chosencurrents X1, X2 and X3. These breakpoints, which have been chosen forillustration, approximate the straightforward nonlinear characteristicll06. It will be noted in FIG. 5 that a mere 4-digit code is used andtherefore that each segment of the characteristic is divided into onlytwo equal portions. it will be recalled that in FIG. 4, where a singlebreakpoint was used in conjunction with a 4-digit code, that eachsegment of the characteristic was broken up into four equal portions.

@nce the currents X1, X2 and X3 have been chosen, the currents i3, isti,igti, and fsw* are chosen to bisect their respective segments, Thefollowing relationships are therefore required if the illustrativepiecewise-linear characteristic of FIG. 5 is to be obtained:

-and

Note that the last expression applies equally well to the embodiment ofFIG. l, in that it also defines the relationship between the binarilyrelated currents of two adjacent subranges of a piecewise-linearcharacteristic having only one breakpoint per quadrant.

As was mentioned in the case of the simple bisegmental piecewise-linearcharacteristic of FIG. 4, it should be understood that it was notnecessary that the characteristic be symmetrically broken in anyquadrant. Thus, for example, the first breakpoint 108 of FIG. 5 need notnecessarily occur at the transition of the third most significant digitof the code. It can be chosen to occur at any desired transition. Itcould, for example, be chosen to occur at the transition of the secondmost significant digit of the code, i.e., at the point where the secondmost significant digit of the code undergoes a transition from 0 to l.

FIG. 6 has been included merely to show one possible way of achievingthe piecewise-linear characteristic of FIG. 5.

Instead of the single resistor RX of FIG. l, three resistors Rm, RX2,and RXS have been used in the circuit of FiG. 6. The values of theresistors RXI, RX2, and RX3 are chosen to supply the currents X1, X2 andX3, respectively, to the reference current lead 26. These resistors maybe switched to the reference current bus 56 by their respective switchesSX1, SX2 and SX3 in any number of ways. Note that the switch-enablinglogic and Hip-flop circuits, fully shown in FIG. I, are not shown inFIG. 6. These circuits may be arranged in accordance with the teachingsinherent in the illustrative embodiment of FlG. l.

In FIG. 5 each breakpoint is shown to be determined by a single currentrather than a combination of currents. Thus, for example, the breakpoint110 is determined, not by a summation of the currents X1, X2 and whatwould be (X3-X2), but rather by a single current X3. This method ofapproximating the breakpoints is perhaps more accurate than would be themethod using the combination of currents mentioned above, in view of thepossibility of cumulative error inherent in the latter method. Thus, inaccordance with the first methodi.e., the method of determining eachbreakpoint by an individual current-if for example, it were necessary tooperate within the range determined by segment lf2, the current X3 wouldbe supplied to the reference current lead 26 to the exclusion ofcurrents X1 and X2. in FIG. 6 this would necessitate the connection ofresistors RXI and RX2 to ground by their respective switches SX1 andSX2, and the connection of resistor RX3 to the reference current bus 56by its associated switch SX3. The various combinations of the currentsX1, X2 and X3, which would be used in the second method discussed above,i.e., the method by which these currents would be used in combination toestablish the breakpoints 110 and 114 of FIG. 5, should be apparent andin need of no further explanation.

The serial resistor R1 of FIG. 6 serves the same purpose as doesresistor R1 of FIG. '1. Also, the function of the shunting resistors R2and R2" is similar to that of shunting resistor R2 of FIG. l.

Refer to FIG. 6A, in which it is assumed for the sake of illustrationthat R2 is of greater magnitude than is Various combinations lof theseshunting resistors can be used to establish the changes in scale factorof FIG. 5.

For example, assume that resistor R3 is connected to the referencecurrent bus 56 by switch S3 so that reference current is fed to juncture100. When the resistor R2" is connected to ground by the switch S2 andthe resistor R2 is connected to the open circuit terminal of switch SZ,the current if* will be supplied to the reference current lead 26. When,however, the resistor R2 is connected to the ground terminal of switchS2 and the resistor R2 is connected to the open circuit terminal ofswitch S2, the current i3dt will be supplied to reference current lead26. When both of the resistor R2' and R2 are connected to ground bytheir respective switches, the current supplied to the reference currentlead 26 by way of the serial resistor R1 will hel isiii, Finally, wheneach of resistors R2 and R2 is connected to its respective open circuitconnection, then the current i3 will `be supplied to reference currentlead 26 by way of resistor R1.

` In' the foregoing description, the invention has been illustrated byapparatus for converting analog information to a binary code. Theinvention may be extended ijn -a straightforward manner to apparatus fortranslating to or from a permutation code of any base b. Thus, for

example, in the case ofthe ternary code in which the e base is 3 andeach digit position may contain a pulse having any one of threecoetiicient values, viz., O, l or 2, the binarily related resistors ofthe reference current circuit 99 of FIG. 1 could be reproportioned sothat the various sums of any number of them taken in succession from areference value are proportional to the successive integral powers of 3.

It should be understood, therefore, that the above describedarrangements are illustrative of the application of the principles ofthe invention. Numerous other arrangements may be devised by thoseskilled in the art without departing from the spirit and scope of theinvention.

What is claimedris:

1. In a system, at one point of which amplitude samples of analogsignals are, throughout the over-all dynamic range of said signals,transformed nonlinearly to groups of pulses arranged in accordance with'a permutation code of base b, nonlinearly meaning that said code doespot vary in direct proportion to said input samples, and at anotherpoint of which said groups of pulses are nonlinearly transformed toreconstitute their original analog form, apparatus to perform saidoverall nonlinear transformations on a piecewise-linear basis whichcomprises means to change the relationship between said amplitudesamples and said permutation code at predetermined transitions in thepermutation of said code, and means to linearly transform said amplitudesamples to said `code and said code to said reconstituted samples onlybetween said predetermined transitions in the permutation of said code,linearly meaning that said amplitude samples and said code, as .wellassaid code and said reconstituted samples, vary in direct proportion toone another, respectively, only between said predetermined transitionsin said code, the over-all relationship between said samples and saidlcode being nonlinear.

2. A system in accordance with claim l in which a preassigned element ofsaid code indicates, in each of said pulse groups, the polarity of theamplitude sample associated with the particular pulse group, means todetermine the polarity of each of said amplitude samples and to generatecorresponding polarity-indicating code elements at said one points ofthe system, and means tov determine the polarity of said elements and toestablish the polarity of said reconstituted amplitude samples at saidother point of the system.

3. A system in accordance with claim 1 wherein said means to linearlytransform said amplitude samples to said permutation code between saidpredetermined.transitions inthe permutation of said code comprises meansto generate reference signals; and means to compare additively saidreference signals with said amplitude samples.

4. A system in accordance with claim 3 wherein said means to lchange therelationship between said ampli- Vtude samples and said permutation codecomprises means to effect a corresponding change in the magnitude ofVsaid reference signals.

l 5. A system in accordance with claim 1 in which said permutation codeis of the base 2, i.e., the binary code, and means to effect saidtransformation between said permutation code and said amplitude samplesin binary fashion.

-6. A system in accordancefwith claim 5 in which the most` significantdigit of said binary code is, in each pulse Ycode group, thepolaritydndicatingdigit, and means to generate said most significantdigitin response to the polarity of the analog signals initiated at saidone point of the system.

7. I n a system, atone pointof which amplitude samples of pulsesarranged in accordance with the binary code and at another point of`which said groups of pulses are non-linearly transformed toreconstitute their original analog form: means to linearlytransform saidamplitude samples to said binary code at said one point of the systemand said binary code to said reconstituted samples at said other pointof the system between predeter mined transitions in the `permutation ofsaid binary code, comprising a timing wave source having a pluralityofroutput terminals related in number tothe number of digits in saidbinary code, a reference current network to generate reference currentof appropriate magnitude and polarity in response to each of saidamplitude samples, a summing network to sum algebraically said referencecurrents and their associated amplitude samples, means to supply saidamplitude samples and said reference currents to said summing network;decision circuit means responsive -to the algebraic sum of each of saidassociated amplitude samples and reference currents to control thegeneration of said reference currents, means to convey said algebraicVsum to the input of said decision circuit, said decision circuit havingan x output-terminal which assumes either of the binary states 0 and 1,depending upon the polarity of said algebraic sum, and an x outputterminal, the bi# nary state of which is the prime of the state of saidx output terminal; means responsive to a binary impulse supplied theretofrom said x output terminal of said decision circuit, and a simultaneoustiming impulse supplied by said timing wave source to said last-namedmeans immediately before the commencement of the second most significantdigit of said binary code, to determine the polarity of said amplitudesamples, said last-named means including a bistable circuit also havingx and x' output terminals, whose respective binary states are dependentupon whether or not said timing impulse and said binary impulse fromsaid x output terminal of said decision circuit are simultaneouslysupplied to said polarity determining means, and a two-position polarityswitch, one position of which is connected to a negative source ofreference potential and the other position of which is connected to apositive source of reference potential, the output of said polarityswitch being connected via said reference current circuit to said meansto supply said reference current to said summing network; and means toperform said nonlinear transformations between said binary code and saidamplitude samples on a piecewise-linear basis which comprises means tochange the scale factor'between said binary code and said amplitudesamples at predetermined transitions in the permutation of said code.

8. A system in accordance with claim 7 in which saidy reference networkcomprises: a pluralityof two-position` .common juncture; a plurality ofscale-factor-changing, twoposition switches each having an output and apair'of inputs corresponding to said two positions, one of said inputsof each of said scale-factor-changing switches being connected to saidpoint of referencepotential and the other of said inputs being connectedto an open circuit terminal, a plurality of shunting resistorscorrespondingVv in number to said plurality of seale-factor-changingswitches, one end of each of said shunting'resistors being connected tothe output of said last-named switches and the other end of eachof saidshunting resistors being connected to said common juncture; a pluralityof switches associated with a corresponding numberof'resistorstodetermine the'loci ofbreakpoints in the coding character- 21 istiedefined by the relationship between said binary code and said amplitudesamples, said breakpoints occurring at said predetermined transitions inthe permutation of said binary code, each of said last-named switchesbeing a twoposition switch having an output and a pair of inputscorresponding tosaid two positions, one of said inputs of each of saidlast-named switches being connected to said point of reference potentialand the other of said inputs being connected to the output of saidpolarity switch, one end of each of said breakpoint-determiningresistors being connected to the output of an associated one of saidlastnamed switches, the other end being connected to said means tosupply said reference currents to said summing network; and means toconnect said common juncture to said other ends of saidbreakpoint-determining resistors.

9. In a system that uses signals in analog form comprising amplitudesamples at one point and, at another point, uses signals in digital formcomprising groups of pulses arranged in accordance with a permutationcode of base b. each of said pulse groups having substantially the sameinformation content as an associated one of said amplitude samples, therelationship between said signal forms defining a pulse code versusamplitude sample characteristic, apparatus for effecting an over-allnonlinear translation on a piecewise-linear basis from one of said formsinto the other form without aleration or' said information content,which comprises means to change the slope of said characteristic atpredetermined transitions in the permutation of said permuted code, andmeans to render said relationship between said pulse code and saidamplitude samples a linear one only between said predeterminedtransitions in said code, said linear relationship meaning that saidcode and-said samples vary in direct proportion to each other onlybetween said predetermined transitions in said code, the over-allrelationship between said code and said samples being nonlinear and saidpulse code versus amplitude sample characteristic thus beingpiecewise-linean 10. An encoder to transform amplitude samples ofcurrent to binary code nonlinearly on a piecewise-linear basis,comprising means to establish a relation between said code and saidcurrent samples defining a piecewise-linear characteristic consisting ofa plurality of segments and at least one breakpoint per quadrant; meansto generate current defining and extending to each breakpoint of saidcharacteristic; means to encode said amplitude samples linearly withineach segmental range of the current axis of said piecewise-linearcharacteristic; and means to change said relation between said amplitudesamples and said code only as the operation of the encoder proceeds fromone segmental range to another, so that said code and said amplitudesamples vary in a unique direct proportion to each other within eachsegmental range.

11. An encoder to transform ampiitude samples of current suppliedthereto to binary code nonlinearly on a piecewise-linear basis,comprising means to establish a relation between said supplied amplitudesamples and said code defining a piecewise-linear characteristic havingat least one breakpoint per quadrant, said characteristic having aplurality of segments per quadrant greater in number by lone than thenumber of breakpoints per quadrant, each of said segments encompassing apredetermined portion of the current axis of said piecewise-linearcharacteristic, means to generate currents defining and extending toeach breakpoint of said characteristic, means to generate additionalcurrent to divide the respective portion of the current axis encompassedby each of said segments binarily in accordance with the number ofelements in said code, means to change said relation between saidamplitude samples and said code only as the operation of said encoderproceeds from one segment to another, means to compare successively witheach of said amplitude samples said breakpoint-determining current andsaid additional currents, means responsive to each of said successivecomparisons to determine which of said breakpoint-determin- 22 ing andsaid additional currents are to be used in the im'- rnediatelysucceeding comparison, and means also responsive to each of saidcomparisons to generate a code element corresponding to the result ofthe comparison.

12. An encoder to transform to binary code, non-linearly on apiecewise-linear basis, amplitude samples of current supplied to theencoder and ranging in absolute magnitude from zero to imax, comprisingmeans to establish a relation between said samples and said codedefining a symmetrical piecewise-linear characteristic having onebreakpoint and two segments per quadrant, each of said segments beingdefined by the breakpoint occurring within its quadrant and eachencompassing a predetermined portion of the current axis of saidpiecewise-linear characteristic, means to generate a current todetermine said breakpoint in each quadrant and having an absolute valueof X, the first segment extending from the origin of each quadrant toits associated breakpoint thereby encompassing X units of said currentaxis, and the second segment extending from said breakpoint therebyencompassing maX*X units of said current axis, means to change therelation between said amplitude samples of said code only as theoperationl of said encoder proceeds from one segment to another, andmeans to encode each of said amplitude samples linearly within thecompass of each of the segments of said piecewise-linear characteristic.

13. An encoder to transform amplitude samples of current to binary codenonlinearly on a piecewise-linear basis comprising means to establish arelation between said code and said samples of current defining apiecewiselinear characteristic consisting of a plurality of segments anda plurality of breakpoints, less in number by one than said plurality ofsegments and determining the eX- tent of each of said segments, means togenerate a plurality of breakpoint-determining currents, means to encodesaid amplitude samples linearly within each segmental range of thecurrentaxis of said piecewise-linear characteristic, and means tolchange said relation between said amplitude samples and said code onlyas the operation of said encoder proceeds from one segmental range toanother, so that said code and said amplitude samples vary in a uniquedirect proportion to each other within each segmental range.

14. An encoder in accordance with claim 13 and means to additivelycombine various combinations of said breakpoint-determiningcurrents todefine each breakpoint of said piecewise-linear characteristic.

15. An encoder in accordance with claim 13 and means to determine eachbreakpoint of said piecewise-linear characteristic by an individual oneof said breakpoint-determining currents, each of said currents therebyextending the entire range from the origin along the current axis ofsaid piecewise-linear characteristic to define its associatedbreakpoint.

16. A coding circuit for nonlinearly converting an amplitude sample of acurrent wave of prescribed amplitude range into binary code on a.piecewise-linear basis which comprises means to generate a sequence ofperiodically recurrent timing pulses; means responsive to the firstpulse of said sequence and to the polarity of said sample to generatethe most significant digit of said code; means responsive to the secondpulse of said sequence and to said most significant digit to develop afirst reference current of predetermined magnitude and of polarityopposite to that of said sample; means to sum algebraically in a firstsummation said sample and said first reference current and also, at thetime of each pulse remaining in said sequence, said sample and allreference currents extant at each of said times; means responsive to thepolarity of said first summation and to said second pulse to generatethe second most significant digit of said code; means also responsive tothe polarity of said first summation and, in addition, to the thirdpulse of said sequence to terminate the generation of said firstreference current only if the polarity of said rst summation is oppositeto that of 2.3 said sample; means responsive to the third pulse of saidsequence and to said second most significant digit to generate a secondreference current of magnitude equal to one-half that of said rstreference current if said iirst reference current has been terminated orto one-half the difference between a predeterminedportion of saidprescribed amplitude range and said rst reference current if the lattercurrent continues to be generated; and means responsive to eachfollowing pulse of said sequence and `to .each following significantdigit to generate further reference currents in the manner by which saidforegoing reference currents were generated.

References Cited in the file of this patent UNITED STATES PATENTSGoodall Nov. 28, 1950 Meacham Apr. 8, 1952 Levy June 9, 1953 Aigrain vNov. 24, 1953 Levine June 11 1957 Slocomb June 17, 1958 Boisvieux Julyl, 1958 Carbrey June 2, 1959

